1. Field of the Invention
The present invention relates generally to a memory device, and more particularly, to a translation look-aside buffer (TLB) for improving performance and reducing power consumption of a memory and a memory management method using the same.
2. Description of the Related Art
In general, a translation look-aside buffer (TLB) is used to reduce memory access time and power consumption and to improve performance of a memory. The TLB is a cache memory having entries for converting virtual addresses to physical addresses.
The TLB is used to reduce average translation time needed in converting addresses in most computers that support paged virtual memory.
There are generally three methods for improving the performance of the TLB. First, a method supporting more entries; second, a method increasing the size of a page; and third, a method supporting multiple page sizes.
However, if the number of entries supported by the TLB increases, latency of memory reference occurs, and if the TLB is implemented by a content addressable memory (CAM), more entries are compared at each reference such that power consumption of the TLB substantially increases.
If the size of a page increases, the coverage of memory mapping increases, but due to increases in internal fragmentation, waste of memory increases, and due to the limited number of pages being mapped, the number of processes is restricted.
Therefore, the best method for improving the performance of the TLB is supporting multiple page sizes. The best among the methods supporting multiple page sizes is receiving predetermined information from the operating system or the compiler and allocating an optimal page size to the TLB. However, this method can apply to the system area of the operating system, but cannot apply to a user area.